1. Technical Field of the Invention
The present invention relates to an active matrix type liquid crystal display, and more particularly to an active matrix type liquid crystal display having a main display area and a sub-display area which have pixel areas different from each other in size respectively.
2. Prior Art
As a conventional active matrix type liquid crystal display, there is known a liquid crystal display shown in FIG. 14. FIG. 14 is a plan view showing a thin film transistor (hereinafter, referred to as TFT) array substrate 140.
On the conventional TFT array substrate 140 for the active matrix apparatus, there are formed respectively: a display area 130 in which pixel areas 132 constituting pixels are arranged in a matrix shape; leader wiring 134 and scanning line terminals 136 for scanning lines for connecting scanning lines 101 in this display area 130 to an external gate driver (not shown); and leader wiring 135 and signal line terminals 137 for signal lines for connecting signal lines 119 in the display area 130 to an external source driver (not shown).
In terms of new functions capable of being added to the conventional active matrix type liquid crystal display, there has been advocated the necessity for providing another display area 31 (hereinafter, referred to as sub-display area) aimed at displaying, for example, character information in addition to a display area 30 (hereinafter, referred to as main display area) as shown in FIG. 1.
In this case, since high definition display is requested for the main display area 30, the pixel area 32 is made small, but in the sub-display area 31, it is not always necessary to cause the size of its pixel area 33 to coincide with that of the main display area because of the display object. Out of requests to display, for example, characters bigger for making them legible, design is made so as to cause the size of the pixel area 33 in the sub-display area 31 to be rather bigger than that of the pixel area 32 in the main display area 30.
On the other hand, in the active matrix type liquid crystal display, a liquid crystal layer is pinched between a pair of substrates oppositely arranged, and this liquid crystal layer is used as a display medium. In order to prevent the liquid crystal layer from being stuck, AC voltage in which DC voltage is not superimposed is applied to the liquid crystal layer, and this is used as display voltage. This AC voltage is applied to a pixel electrode mainly constituting the pixel area from the signal line through TFT which has turned ON through gate voltage from the scanning line. A steady DC voltage is applied to an opposite electrode which opposes to this pixel electrode through the liquid crystal layer. Thus, an electric field is imparted to the liquid crystal layer to change its refractive index whereby the liquid crystal layer becomes usable as a display medium.
However, a dynamic voltage drop xcex94Vp occurs in potential Vp of the pixel electrode when the gate voltage is changed in order to cause TFT to be in an OFF state, resulting from: a change in the dielectric constant of the liquid crystal in response to the field intensity; existence of parasitic capacity between gate electrode and drain electrode of TFT; existence of parasitic capacity between scanning line and pixel electrodes sandwiching insulating film therebetween; existence of parasitic capacity between scanning line and capacity electrodes sandwiching insulating film therebetween; existence of parasitic capacity between signal line and pixel electrodes sandwiching insulating film therebetween; existence of parasitic capacity between signal line and capacity electrodes sandwiching insulating film therebetween; and the like.
When the gate voltage Vg is caused to change in order to cause TFT to be in an OFF state, a dynamic voltage drop xcex94Vp occurs in potential Vp of the pixel electrode. When the gate voltage Vg is caused to change in order to cause TFT to be in an OFF state, electric charge is distributed between capacity of the liquid crystal layer between a pair of substrates, storage capacity consisting of the scanning line, gate insulating film thereon and capacity electrode, and the parasitic capacity to cause a voltage drop xcex94Vp in the potential Vp of the pixel electrode.
When the voltage drop xcex94Vp occurs in the potential Vp of the pixel electrode as described above, a difference will occur between positive and negative voltage amplitudes at the potential Vp of the pixel electrode for driving the liquid crystal with center potential Vsc of the signal voltage Vs as a reference. If the same voltage is applied irrespective of the polarity of voltage, the liquid crystals have the same transmittance characteristic. Therefore, in, for example, a normally white, active matrix type liquid crystal display having high transmittance in a no-voltage applied state, it becomes lower in transmittance in polarity having a large voltage amplitude, and higher in polarity having a small voltage amplitude. For this reason, light and dark responsive to the transmittance are repeated, and these will be visually identified as flickers.
Variations in the dielectric constant of the liquid crystal, which is one factor for causing the voltage drop, in response to the field intensity relate to the physical properties of the liquid crystal and cannot be avoided. Also, as another factor, there are parasitic capacity of circuits, of which, existence of parasitic capacity between gate electrode and drain electrode of TFT cannot be structurally avoided in the current active matrix type liquid crystal display because gate insulating film formed between the electrodes forms capacity.
Also, the parasitic capacity between scanning line and pixel electrode cannot be structurally avoided in the current active matrix type liquid crystal display.
Thus conventionally, the potential at the opposite electrode is adjusted at the optimum such that the positive and negative voltage amplitudes for AC voltage for driving the liquid crystal are equal to each other, and the storage capacity is formed in parallel with respect to the capacity of the liquid crystal layer, whereby an attempt has been made to resolve the flickers.
Where there is, in addition to the main display area, provided a sub-display area having a pixel area different in size, there occurs a difference in voltage drop xcex94Vp of pixel electrode between the main and sub-display areas because the value of the liquid crystal capacity or the parasitic capacity differs depending upon the size of the pixel area. This has led to a problem that flickers become prone to be visually identified to deteriorate the display quality.
The present invention has been achieved in order to solve the above-described problems, and is aimed to provide an active matrix type liquid crystal display capable of preventing flickers from occurring by applying the same potential to the opposite electrode without dividing the opposite electrode between main and sub-display areas which have pixel areas different in size respectively.
An active matrix apparatus according to the present invention is constructed such that there is sandwiched a liquid crystal layer between a pair of substrates oppositely arranged; on the surface of one substrate, a plurality of scanning lines and a plurality of signal lines are formed to intersect each other in a matrix shape; in the vicinity of a plurality of intersected portions formed by the plurality of scanning lines and signal lines, there are formed respectively TFTs having gate electrodes connected to the scanning lines, pixel electrodes connected to the TFTs, and capacity electrodes for forming storage capacity with the scanning lines and the storage capacity; on the surface of the other substrate on the liquid crystal layer side, there is formed an opposite electrode; there are provided a main display area having a plurality of pixel areas, each of the pixel areas being enclosed with the scanning lines and the signal lines and being equal to one another, and a sub-display area having pixel areas different in size from the pixel areas in the main display area having the plurality of pixel areas; and a ratio of minimum space between each pixel electrode, the scanning line for driving it and the gate electrode in the sub-display area, to the maximum space between opposite surfaces of paired substrates is set to one or more.
According to such a liquid crystal display, it is possible to reduce parasitic capacity Cgp (hereinafter, referred to as Cgp) between the pixel electrode, the scanning line and the gate electrode in the sub-display area, to ignore any influence on the voltage drop xcex94Vp of the pixel electrode in the sub-display area due to this parasitic capacity, and to deduct one of design parameters concerning the voltage drop xcex94Vp of the pixel electrode in the sub-display area. As the design parameters for the voltage drop xcex94Vp, there are storage capacity Cs and parasitic capacity Cgd (hereinafter, referred to as Cgd) between the gate electrode and the drain electrode of the TFT in addition. Of these, Cgd varies depending upon the channel width W and channel length L of the TFT, but a ratio of the minimum space between pixel electrode, scanning line and gate electrode, to the maximum space between opposite surfaces of the paired substrates is set to one or more. If Cgd cannot be ignored, xcex94Vp cannot be designed by handling each of them as an independent parameter because Cgp also varies with Cgd. For this reason, since it becomes possible according to such a liquid crystal display to ignore the Cgp, it becomes easy to design the xcex94Vp, and it is possible to design such that the main and sub-display areas having pixel areas different in size respectively have xcex94Vp in common, and therefore, to make potential at the opposite electrodes identical.
A maximum space between each pixel electrode, scanning line for driving it and gate electrode in the sub-display area is preferably set to a smaller value than a value obtained by deducting the length of the pixel electrode in the main display area in a direction perpendicular to the scanning line thereof from the length of the pixel electrode in the sub-display area in a direction perpendicular to the scanning lines thereof. This is because it becomes possible to make the potential at the opposite electrodes identical for the above reason, and the aperture ratio of the sub-display area is made larger than that of the main display area.
Another active matrix type liquid crystal display according to the present invention adopts, in an active matrix type liquid crystal display having main and sub-display areas having pixel areas different in size respectively, means for preventing flickers and sticking from occurring by making voltage drop xcex94Vp of the pixel electrode equal to each other between the main and sub-display areas with respect to the identical opposite electrode potential without dividing the opposite electrode.
According to the present invention, there is provided an active matrix type liquid crystal display, in which there is sandwiched a liquid crystal layer between a pair of substrates oppositely arranged; on the surface of the one substrate, a plurality of scanning lines and a plurality of signal lines are formed to intersect each other in a matrix shape; in the vicinity of a plurality of intersected portions formed by the scanning lines and signal lines, there are formed respectively: TFTs having gate electrodes connected to the scanning lines, pixel electrodes connected to the TFTs through drain electrodes, and capacity electrodes for forming storage capacity with the scanning lines; and there are constituted a main display area and a sub-display area having pixel areas different from each other in size respectively, each of the pixel areas being enclosed with the scanning lines and signal lines, while on the surface of the other opposite substrate on the liquid crystal layer side, there is formed an opposite electrode, wherein there is adopted, as one means, a method for changing the storage capacity of the TFTs by making the channel widths of the TFTs different between the main and sub-display areas. As another means, there is adopted a method for constituting so as to make the storage capacity different between the main and sub-display areas.
A voltage drop xcex94Vp of potential at the pixel electrode 11 can be expressed by the following equation (1):
xcex94Vp=(Vghxc3x97(Cgdon+Cgp)xe2x88x92Vglxc3x97(Cgdoff+Cgp)xe2x88x92Vs(Cgdonxe2x88x92Cgdoff))/(Cs+Clc+Cgdoff+Cgp)xe2x80x83xe2x80x83(1)
where
xcex94Vp: Voltage drop of potential at pixel electrode
Vgh: High potential of gate voltage
Cgdon: Parasitic capacity when TFT is ON
Cgp: Parasitic capacity between scanning line and pixel electrode
Vgl: Low potential of gate voltage
Cgdoff: Parasitic capacity when TFT is OFF
Vs: Potential of signal voltage
Cs: Storage capacity
Clc: Capacity of liquid crystal layer
As shown in the equation (1), as factors for causing the voltage drop xcex94Vp of potential at pixel electrode, the capacity Clc of liquid crystal layer, the parasitic capacity Cgd of TFT, the storage capacity Cs and the like are included.
When the sub-display area has a larger pixel area and the capacity Clc of the liquid crystal layer becomes larger in the equation (1), the voltage drop xcex94Vp becomes smaller. The parasitic capacity Cgp between the scanning lines and the pixel electrode is capacity to be formed by a non-uniform electric field, and therefore, it is difficult to adjust the value in design. In order to recover the voltage drop xcex94Vp, there can be conceived a method for causing the voltage drop xcex94Vp not to become smaller by making the parasitic capacity Cgdon of the TFT larger or the storage capacity Cs smaller. If the voltage drop xcex94Vp does not change, voltage amplitudes based on positive and negative polarities in FIG. 4(c) will become equal to each other, thus making it possible to prevent flickers and sticking. Conversely, in the main display area having a smaller pixel area in size, the parasitic capacity Cgd of the TFT can be made smaller or the storage capacity Cs can be made larger.
A fluctuation xcex94Vp in the pixel electrode potential depends also upon fall delay time of the gate signal. When the gate voltage is cut off to cause the TFT to be in an OFF state in FIG. 6(a), the voltage is not cut off in an acute-angled rectangle shape as indicated by solid line, but exponentially fluctuates as indicated by broken line to generate delay time (t) before the voltage disappears. If the fall delay time (t) of the gate signal is large, the TFT will not become completely OFF, and therefore, electric charge leaks from the pixel electrode through the TFT to cause the fluctuation in the pixel potential. If the voltage were cut off originally like an acute angle when the gate signal is caused to be in an OFF-state, such xcex94Vp as indicated by solid line would occur in FIG. 6(c), and when delay time (t) is caused, the xcex94Vp becomes smaller to become xcex94Vpxe2x80x2. This delay time (t) varies with various factors such as pixel capacity, wiring capacity or wiring resistance. Therefore, the main and sub-display areas having pixel areas different in size respectively become different also in the delay time (t), and therefore become different also in the xcex94Vpxe2x80x2.
Further, the delay of the scanning signal affecting the voltage drop xcex94Vp of the pixel electrode is determined by the wiring resistance and wiring capacity of the scanning lines. Assuming the wiring resistance of the scanning lines to be Rg and the wiring capacity thereof to be Cg, a time constant T of the scanning lines is expressed as the product of Rg and Cg.
That is, T=Rgxc3x97Cgxe2x80x83xe2x80x83(2)
This time constant T represents delay in the scanning signal, if both areas are equal in time constant T irrespective of the size of the pixel area, they will also become equal in signal delay, and accordingly also in xcex94Vpxe2x80x2 of FIG. 6(c). When, however, the size of the pixel area changes, the Cg changes, and the time constant also changes. Accordingly, as a countermeasure against flickers in a liquid crystal display having main and sub-display areas having pixel areas different in size, there is posed a problem how time constants T of each display area should be made equal to each other.
The Rg and Cg are values obtained by composing all resistance and capacity connected to the scanning lines respectively. In other words, as Rg component, wiring resistance is included in wiring resistance of the scanning lines themselves and the leader wiring. Also, as Cg component, there are included series capacity of liquid crystal layer capacity Clc and storage capacity Cs, parasitic capacity Cgds between gate electrode and drain electrode of TFT, and gate electrode, parasitic capacity Cgp between scanning lines and pixel electrodes, parasitic capacity Cx between scanning lines and signal lines and the like. Since these capacities constitute parallel capacity, the following relation is established:
Cg=(Clcxc2x7Cs)/(Clc+Cs)+Cgds+Cgp+Cxxe2x80x83xe2x80x83(3)
In this case, when the size of the pixel area is small, the Clc becomes small, and the first term in the right-hand side of the equation (3) becomes small. If the Cg becomes smaller, T will become smaller from the equation (2). Therefore, in order to keep t constant, the Rg can be made larger from the equation (2), or the Cg can be made not smaller.
In order to make both areas equal in delay in the scanning signal as described above, there is a method, as one means, for making the main and sub-display areas different from each other in wiring resistance of the scanning lines. As another means, there is a method for making the main and sub-display areas different from each other in wiring capacity of the scanning lines by constituting these areas such that they are different in the area of the portion where the scanning lines and the signal lines overlap.
By adopting such a method as described above, it becomes possible to make the main and sub-display areas having pixel areas different in size respectively equal to each other in delay time (t) of the gate signal, and to design such that both have voltage drop xcex94Vp, in common, affected by delay in the gate signal. Therefore, voltage amplitudes based on positive and negative polarities can be made equal to each other and sticking and flickers can be prevented.
In other words, in FIG. 6(c), the main and sub-display areas are caused to have the fall delay time (t) of the gate voltage in common, and to have voltage amplitudes, in common, due to positive and negative polarities without changing the potential at the opposite electrode.